Semiconductor Engineering

Dual Instruction-Set Architecture, Supporting A TTA And RISC-V Instruction Set Via a Lightweight Microcode Hardware Unit

A technical paper titled “Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode” was published by researchers at Tampere University. “Transport triggered architectures ...
Semiconductor Engineering

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases

This new technical paper titled “Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms” was published by researchers at Intel, North Arizona University and Google, with ...
TechSpot

Intel proposes the x86-S architecture for a simpler, more efficient CPU instruction set

Forward-looking: After being beaten by AMD in introducing the first, truly 64-bit instruction set in the x86 CPU world, Intel is now trying to get ahead of its historical competitor by working on a ...
Electronic Design

RISC-V Serves Up Open-Source Possibilities for the Future

What is RISC-V? The basics of RISC-V. Applications and uses of RISC-V. RISC-V is described as an open standard instruction set architecture (ISA) that's based on the reduced instruction set computer ...